1. Field of the Invention
The invention relates to pipelined analog-to-digital converter (ADC), and more particularly to pipelined analog-to-digital converter having a plurality of stages sharing an operational amplifier.
2. Description of the Related Art
A pipelined analog-to-digital converter converts an analog input signal to a digital output signal. Referring to FIG. 1, a block diagram of a conventional 10-bit pipelined analog-to-digital converter 100 is shown. The conventional 10-bit pipelined analog-to-digital converter 100 converts an analog input signal Vin into a 10-bit digital output value Dont. In one embodiment, the pipelined analog-to-digital converter 100 comprises a sample and hold circuit 101, a first stage 102, a second stage 104, a third stage 106, a 4b flash circuit 107, and a digital correction module 108. The sample and hold circuit 101 samples and holds an analog input signal Vin of the pipelined analog-to-digital converter 100. The sampled analog input signal is then delivered to the first stage 102.
The first stage 102, the second stage 104, and the third stage 106 are connected in series. Each stage receives a stage input signal from a prior stage, derives a stage output value and a residue from the stage input signal, and outputs the residue to a subsequent stage as the stage input signal of the subsequent stage. For example, the second stage 104 receives a residue from the first stage 102 as a stage input signal, and the third stage 106 receives a residue from the second stage 104 as a stage input signal. The 4b flash circuit 107 converts the residue of the third stage 106 to a residue. The digital correction module 108 then generates a digital output value Dout according to the stage output values D1, D2, and D3 of the first stage 102, the second stage 104, and the third stage 106 and the residue of the 4b flash circuit 107.
The three stages 102, 104, and 106 have the same circuit structure. Each of the stages 102, 104, and 106 comprises a multiplying digital-to-analog converter (MDAC) and a 2.5b sub ADC. Referring to FIG. 2A, a block diagram of a stage 102/104/106 of the conventional pipelined analog-to-digital converter 100 is shown. In one embodiment, the stage 102/104/106 comprises a MDAC 202 and a sub ADC 204. A stage input signal Vin of the stage is sent to the sub ADC 204 and the MDAC 202. The sub ADC 204 converts the stage input signal Vin from analog to digital to obtain a stage output value D. The MDAC 202 comprises a digital-to-analog converter (DAC) 212, a subtractor 214, and an amplifier 216. The DAC 212 converts the stage output value D from digital back to analog to obtain an analog signal D′. The subtractor 215 subtracts the analog signal D′ from the stage input signal Vin to obtain a difference signal. The amplifier 216 then amplifies the difference signal to obtain the residue Vres. The residue Vres of the stage is then output to a subsequent stage as a stage input signal.
The function of the MDAC 202 is generally implemented with an operational amplifier. Referring to FIG. 2B, a circuit diagram of an operational amplifier 252 used by the stage is shown. A capacitor 254 alternately samples the stage input signal Vin and the analog signal D′, and a capacitor 256 is coupled between the negative input terminal and an output terminal of the operational amplifier 252 for amplifying the difference signal to obtain the residue Vres. The output terminal of the operational amplifier 252 outputs the residue Vres of the stage.
As the conventional pipelined analog-to-digital converter 100 comprises three stages 102, 104, and 106, and each of the stages 102, 104, and 106 comprises a MDAC 112, 122, and 132, the conventional pipelined analog-to-digital converter 100 requires three operational amplifiers to implement the function of the MDAC 112, 122, and 132. The power consumption of an operational amplifier, however, is high, and three operational amplifiers for the three stages 102, 104, and 106 results in a large amount of power consumption for the conventional pipelined analog-to-digital amplifier 100, which degrades the performance of the conventional pipelined analog-to-digital amplifier 100. Thus, a pipelined analog-to-digital amplifier 100 with reduced power consumption is required.